The present invention relates generally to the fabrication of complementary insulated gate field effect transistors (commonly referred to as a CMOS FET or CMOS Device) and, more particularly, to a process of fabricating high density complementary insulated gate field effect transistors (HCMOS FETs) having conductively interconnected wells.
The well-known CMOS FET device is typically composed of a closely spaced and appropriately interconnected pair of n-channel and p-channel field effect transistors. The CMOS device is usually fabricated on an n-type semiconductor substrate, with the p-channel transistor being formed at the surface of the substrate and the n-channel transistor being formed at the surface of a p-type layer (p-well) doped into the substrate. The n and p-type transistors are then interconnected by polysilicon and metalization layers to form a CMOS FET device. As a building block for much larger and more complex integrated circuits, CMOS FETs provide a number of notable advantages including high noise immunity, low power-speed product, and near zero standby power requirement.
One significant disadvantage to the use of conventional CMOS devices in large scale integrated (LSI) circuits is that they inherently require a greater amount of substrate surface area than either functionally equivalent n- or p-channel FET devices. For example, the CMOS device density in an integrated circuit can be up to 40% less than the device density achieved by using conventional n-MOS technology.
This size disadvantage is directly related to the amount of substrate surface area required by each p-well. Naturally, the well surface must be sufficient to allow for alignment and processing latitudes in the CMOS fabrication procedure, thereby ensuring that the n- and p-channel transistors are suitably situated with respect to the p-well. However, in conventional CMOS devices, it must also be sufficient to allow for an electrical contact, separate from the n-channel transistor, to be placed on the well surface. This contact, further connected to an appropriate voltage potential source, is required in order to electrically isolate the well from the substrate by reverse biasing the well/substrate junction.
Another disadvantage arises when LSI CMOS devices are used in high voltage applications. In order to increase device density as much as possible, the parasitic channel stop associated with each transistor is allowed to overlap the transistor's source and drain regions. As is well known, channel stops are necessary to prevent the formation of parasitic channels between neighboring transistors. Typically, the channel stops are highly doped regions formed in the substrate surrounding each transistor and effectively block the formation of parasitic channels by substantially increasing the substrate's surface inversion threshold voltage. Also, they are by necessity the opposite in conductivity type from the source and drain regions they overlap in order to prevent shorting. This, however, results in the formation of highly doped and, therefore, low reverse breakdown voltage p-n junctions. Consequently, the maximum operating voltage potential of the CMOS integrated circuit is significantly limited.